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CCD controller of the national telescope Galileo

The Italian National Telescope "Galileo" (TNG) will support a large set of visual and near IR detectors at the focal plane. In order to drive efficently these detectors a set of specific controllers with shared hardware and software are developed. The aim of the project is to simplify the observations and have an easy maintenance of the whole system. The CCD controller for the Telescopio Nazionale Galileo (TNG) is a modular system based on Digital Signal Processing (DSP) and Transputer Modules (TRAM) that uses a customized bus based on VME BUS, named CCDC-BUS. The CCD controller is interfaced with an host computer (PC or Unix workstation) via optical fibre. The architecture of the whole controller has been designed to allow a very easy expansion.

CCD Camera Controller Main Features

For the TNG focal plane we can use two types of CCD: the Loral tree-side buttable CCDs with a 2048X2048 pixel format (15 micron pixel size) and the EEV CCDs with 4096X2048 pixel format (13.5 micron pixel size) CCDs . Each CCD can be read from two outputs. The controller is able to drive a 2X2 mosaic for LORAL CCD and a 2X1 mosaic for the EEV CCD. The readout time in both cases is the same as that needed to read a single chip. The image is at once reformatted in order to simulate a single sensor having the full mosaic size. This task is executed by one of the transputer of the system. Three boards constitute the entire controller: the Sequencer that provides the digital signals, the analog board and the preamplifier

CCD Sequencer

The Sequencer provides different selectable readout speeds useful to optimize the CCD noise figure. The CCD Sequencer performs the following tasks:

  • generate the clock waveforms and the signals for the video processor
  • handle the local data-buffer
  • provide the data telemetry
  • handle commands sent by the host
  • drive the shutter and the temperature-controller
    Programmed waveforms are generated with a minimum of 100 ns per state. The CCD can be readout in various modes:

  • full frame
  • set of predefined boxes with fast skip of unwanted pixels
  • with binning
  • drift & scan
    Synchronization can be externally obtained when the CCD readout mode is the drift & scan. The heart of the CCD Sequencer is a standard TRAM module (DTM560) containing a couple of high speed processors: a 16-bit T222 transputer and a 24-bit 56001 MOTOROLA DSP. The transputer and DSP communicate data and application SW through a set of shared memory locations. Thanks to the simple reconfigurable networking scheme, embedded on the transputer, fast communication of data and commands can be easily implemented with little extra hardware. The CCDC Sequencer (CCDSEQ) is mounted on a double eurocard (160 X 234 mm). This board acts also as motherboard for three standard TRAM service slots. Part of the electronics dedicated to the generation of programmable sequences from the DSP is directly mounted on the motherboard. The DTM560 TRAM module is a customized version,which allows the DSP bus to be used outside the board. Communication between the DSP bus and the motherboard is obtained through a couple of sockets, one placed on the TRAM side and the other one on the motherboard side. External communication is obtained through the transputer link 0 which is carried by the TRAM slot 1 and then converted to an optical fibre link. The TRAM slot 2 is always filled by the PST207 TRAM module, holding a four optical fibre communication system. TRAM slot 3 can be linked to other TRAM expansions. Link 1 and link 2 coming from DTM560 are connected in daisy-chain with the controller BUS and thus external TRAM modules can be mounted on expansion cards. All communication functions are supported by the DTM560 T222 transputer through links (with the exception of DSP communication which is memory mapped), while the generation of sequences is supported by the DSP. In particular the transputer performs:
  • the boot of executable programs (transputer and DSP)
  • the handling of optical fibre communication (commands, telemetry and data)
  • the data exchange and the dispatch of commands to DSP
  • the collection of data from ADCs and transmission to the root system
  • the communication with expansion TRAMs.
    The DSP performs:
  • the generation of sequences
  • the execution of commands from the T222.
    Sequences can be generated in two DSP ports: PORT A that provides 16 independent Sequencer status lines and PORT B that provides 12 independent Sequencer status lines. The status and the delay loop are derived from a given table. The upper 8 bits of the DSP 24-bit word are used to set an 8 bit counter, the lower 16 bits are used as programmable Sequencer lines. The counter holds the DSP in WAIT state until the counter rolls over. A maximum delay of 25.6 micro seconds can be programmed because each tick is 100 ns. Longer delays, when needed, can be obtained through conventional SW loops. The DSP circuit is complemented by:
  • a card ID selector (8 readable dip-switches)
  • an external opto-coupled sync port
  • a programmable front panel LED
  • a switch to select the use of the X or Y DSP bus for CCD functions
  • an address decoder to handle internal and external memory.
    The card ID selector can be used by the transputer when various CCDSEQ are connected on the network. The external sync port can be used to force CCD readouts (full frame or one line at a time) following an external signal (i.e. drift & scan operation). The optical fibre link is handled by a size two TRAM module that carries one of the selectable transputer links (link 0 or 1 or 2 or 3) and the NOT-ERROR, ANALYZE and RESET signals. A companion module is mounted on the host computer.


    The preamplifier, located close to the cryostat, is a four input differential amplifier based on a low noise operational amplifier (OPA 627). The board is made with a surface mount technology and it stabilizes the power supply. The gain of each channel is set to 35 (the total gain from CCD to ADC is about 70) in order to obtain a conversion factor of 1e-/ADU. The Clamp signal is optocoupled to minimize the digital noise.

    The Analog Board

    The analog board can be divided into four logic blocks:
  • The Control Logic
  • The Programmable Bias Generator
  • The Clock Driver
  • The Correlated Double Sampler (CDS)

    Control Logic

    This section is a piggy-back module containing a T225, 32 Kbytes memory and a Programmable Gate Array (Xilink) and it manages the internal logic and data collection. The following actions are performed:
  • card address decoding
  • driving of A/D converter
  • local memory management
  • preamplifier gain control
  • status display control (led mounted on board)

    Programmable Bias Generator

    The block that generates the Bias levels has the following features:
  • 8 output voltages programmable through 12-bit D/A converters (quad D/A converters with serial loading)
  • voltages buffering through operational amplifiers
  • level converter using a voltage divider at each operational amplifier output for telemetry
  • a 8/1 multiplexers allowing the choice among 8 analog signals
  • telemetry of the bias voltages through a 16-bit ADC (CS5101 Crystal)
    The board is a double eurocard and is made by using the Surface Mount technology. Furthermore the board provides accurate reference voltages generator for the on board DACs, ADCs, and OPAMPs. The voltage levels monitoring is based on the same ADC used for CCD data acquisition (CS5101 Crystal). All steady voltage levels are programmable and monitored. A telemetry cycle can be repeated at a programmable rate. The generated voltages are:
  • 4 bipolar voltages in the range -12/+12 Volts (5 mA)
  • 3 unipolar voltages in the range +10/+20 Volts (5 mA)
  • 1 unipolar voltage in the range +20/+30 Volts (40 mA)

    Clock Driver

    The clock driver block performs the level shift and buffering of signals coming from the Sequencer. Low and high levels are programmable and their values are monitored by telemetry. The circuit used for the voltage level generation is similar to the bias generator block but it uses two octal D/A converters with serial loading (DAC 8800 PMI). Fast switches (DG403) and buffer (LM324) are used to drive the CCD. To introduce fixed rise and fall time, a resistor-capacitor circuit is used. The voltages are monitored in the same way as the bias.

    Correlated Double Sampler

    To filter the video signal from noise of high and low frequencies, the baseline and the CCD output are integrated and subtracted by the correlated double sampler (CDS). The correlated double sampler can operate in two modes:
  • Video signal and baseline are integrated for a fixed period of time and after the difference between both signals is made. The difference is converted by the ADC.
  • Both signals are integrated and converted separately and the binary difference is performed by transputer. The CDS is made up of four parts: the first one (see figure) is an analog switch that inverts the input signal. The second one is a very low-noise differential instrumentation amplifier (gain=2). The third part integrates the signals, and the last part allows us to add an offset level to a given signal in order to adapt it to the voltage range of the ADC module. The ADC (16 bit 100 KHz CS5101 Crystal) converts and sends the data to the transputer. < ALIGN=left WRAP=on>

    Software Architecture

    The software, with the exception of dedicated parts (for instance the DSP SW), largely depends on the selected support architecture (WS, nets, crates, displays that support a given application). There are some different hardware platforms:
  • system development
  • applicative system for small arrays
  • applicative system for large arrays
    A system based on a PC fulfills the first two features, while for the third one a more powerful Workstation must be used. The simplest system used is that made up by a PC 386 (4 MBytes RAM), an INMOS B008 board, a master TRAM module on the B008, an optical fibre adapter on the B008 (for instance the PARATECH PST207) and a second PST207 optical fibre adapter on the CCD controller. The software tools are based on the INMOS OCCAM TOOLSET (version D7205A) the MOTOROLA DSP development system, the PERIMOS DTM560 toolbox, the MS-DOS WINDOWS-3 and the transputer WINDOWS FILE SERVER. The controller configuration is ``host-independent'', which means that it can be mounted on different TRAM-support boards (i.g. VME boards) and can be linked to more powerful hosts. The software architecture is sketched in the Figure. Three groups of procedures operate:
  • the ROOTER based on the TTG3/T8 transputer
  • the SLAVE and SLAVE1 based on the DTM/T2 and ANALOG/T2 transputers
  • the KERNEL56 based on the DTM/56001 DSP
    There are three groups of communication channels:
  • the FS/TS channels from/to HOST-PC/ROOTER
  • the ROOT.DTM/DTM.ROOT channels from/to ROOTER/SLAVE and ROOTER/SLAVE1
  • the IO channel from/to SLAVE/KERNEL56 and from/to SLAVE1/KERNEL56
    The ROOTER group of procedure is made by a user interface (USER.IF) which accepts commands and displays telemetry, a command sender procedure (SEND.CMD) which communicates with the SLAVE through the ROOT.DTM channel, a telemetry receiver procedure (GET.TLM) which takes data from DTM.ROOT channel. On the SLAVE side there are two procedures (IN.PROCESS and OUT.PROCESS) plus the handler of communications with KERNEL56 (IO). The above mentioned procedure, except for the KERNEL56, which is written in 56001 assembler, is written in OCCAM and loaded by the standard INMOS ISERVER. Commands and telemetry are transmitted through buffer structures.

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